1. Field of the Invention
The present invention relates to an image display apparatus employing a grid-like matrix of display elements, such as a liquid crystal panel display, a plasma display, an EL display, or the like, and more particularly to an image display apparatus to be connected to a video signal source for outputting a video signal such as an RGB video signal and a high-definition video signal.
2. Description of the Related Art
There are known image display apparatus employing a grid-like matrix of display elements, such as a liquid crystal panel display or the like.
The image display apparatus of the above type is connected to a video signal source such as a personal computer, a workstation, or the like, and is capable of displaying an image based on a video signal supplied from the video signal source.
The video signal source supplies the image display apparatus with a video signal whose signal level changes at a constant frequency (hereinafter referred to as “dot clock”) that is higher than the frequency of a horizontal synchronizing signal representing the display period in a horizontal direction of a displayed image. The image display apparatus reproduces a dot clock having the same frequency as the dot clock in the video signal source, and displays an image based on the video signal from the video signal source based on the reproduced dot clock. The dot clock reproduced in the image display apparatus will be referred to as “reproduced dot clock”. The image display apparatus has a PLL (Phase Locked Loop) circuit, and can adjust the frequency of the reproduced dot clock so as to be an integral multiple of the frequency of the horizontal synchronizing signal for the video signal supplied from the video signal source, by changing the frequency-division ratio of the frequency divider of the PLL circuit.
If the dot clock frequency (or the frequency-division ratio) in the video signal source is known, the frequency of the reproduced dot clock can accurately be equalized to the dot clock frequency in the video signal source by setting the frequency-division ratio of the PLL circuit according to the known dot clock frequency.
If the input video signal is an analog signal, however, no information is available as to the dot clock supplied from the video signal source to the image display apparatus, and only a horizontal synchronizing signal and a vertical synchronizing signal are provided as timing information. Since the image display apparatus cannot acquire, in advance, the dot clock frequency (or the frequency-division ratio) in the video signal source, there is no guarantee that the frequency-division ratio of the frequency divider of the PLL circuit will be set to a correct value. If the frequency-division ratio is not set to a correct value, then since the frequency of the reproduced dot clock is not in agreement with the frequency of the dot clock in the video signal source, a deviation occurs between the reproduced dot clock for capturing the video signal and the video signal, with the result that the image cannot properly be displayed.
The user itself may be able to adjust the frequency of the reproduced dot clock while watching the displayed image, using an adjustment function of the image display apparatus. However, it is highly tedious and time-consuming for the user to manually adjust the frequency of the reproduced dot clock.
There has been proposed an apparatus for automatically adjusting the frequency of the reproduced dot clock.
Japanese patent No. 3487119 (hereinafter referred to as “Patent Document 1”) discloses a dot clock reproducing apparatus having an A/D converter for converting an input video signal (analog) supplied from a video signal source into a digital signal, a PLL circuit for generating a clock in synchronism with the horizontal synchronizing signal of the input video signal, a frequency analyzing means for detecting an aliasing frequency which is produced when the input video signal is converted into a digital signal with a sampling clock that is different from the dot clock of the input video signal, and a frequency-division ratio setting circuit for setting a frequency-division ratio of the PLL circuit depending on the aliasing frequency detected by the frequency analyzing means. The disclosed dot clock reproducing apparatus automatically adjusts the frequency of the reproduced dot clock so as to minimize the aliasing frequency, without the need for manual frequency adjustment.
A process of automatically adjusting the frequency of the reproduced dot clock is also disclosed in U.S. Pat. No. 5,767,916 (hereinafter referred to as “Patent Document 2”) in addition to Patent Document 1.
According to Patent Document 2, the frequency of a horizontal synchronizing signal that is supplied simultaneously with an analog video signal (RGB) is measured, and the number of lines during one frame is counted. From the frequency of the horizontal synchronizing signal and the number of lines during one frame, a table is referred to for estimating the horizontal resolution of the analog video signal and the frequency of the dot clock, and a horizontal display interval E of the analog video signal and a frequency-division ratio n are temporarily established. Then, a horizontal display interval W of the actually captured video signal is determined. If W<E or W>E, a new frequency-division ratio n′ is determined according to the equation n′=n×E/W and then the same measurement is carried out with respect to the following frame. If W=E, then it is judged that the frequency of the reproduced dot clock is accurately adjusted, and the automatic adjusting process is put to an end.
However, even when the frequency of the reproduced dot clock is accurately adjusted, if the phase of the video signal and the reproduced dot clock is not properly adjusted, then the display image suffers fluctuation and flickering. This problem will specifically be described below.
A reproduced dot clock generated by a PLL circuit suffers fluctuation (jitter) on the time axis. Jitter is determined by a time constant circuit such as a loop filter or the like of the PLL circuit. Since a tradeoff generally exists between jitter and response speed, it is difficult to eliminate jitter. Since the reproduced dot clock suffers jitter of necessity, even when the frequency of the reproduced dot clock is in agreement with the frequency of the dot clock in the video signal source, if the phase of the reproduced dot clock is not correct, then it is difficult to display the image stably. The reasons for this problem will specifically be described below.
FIG. 1 of the accompanying drawings shows the manner in which the phase relationship between an input video signal and a reproduced dot clock is correctly adjusted, and FIG. 2 of the accompanying drawings shows the manner in which an input video signal and a reproduced dot clock are out of phase with each other. The video signal shown in FIGS. 1 and 2 represents a portion of one line displayed on the screen, and has its signal level varying according to the dot clock in the video signal source. In the example shown in FIGS. 1 and 2, the video signal includes a succession of signals having different signal levels, e.g., nth signal 32, (n+1)th signal 34, (n+2)th signal 35. Changing points 33 whose levels change gradually are present between signals 32, 34, 35.
The phase of reproduced dot clock is in agreement with negative-going edges, for example, of the horizontal synchronizing signal of the input video signal. The frequency of the reproduced dot clock is represented by an integral multiple of the horizontal synchronizing signal (the frequency-division ratio). No phase comparison is possible from a negative-going edge to a next negative-going edge of the horizontal synchronizing signal. Therefore, fluctuation on the time axis, called jitter, occurs on positive-going edges of the reproduced dot clock. A positive-going edge of the reproduced dot clock is present somewhere in jitter area 31, but its position cannot be located because it varies from line to line and from frame to frame.
In FIG. 1, since jitter area 31 of the reproduced dot clock is positioned in a stable level portion of the video signal, the video signal can be sampled correctly regardless of the position of the positive-going edge in jitter area 31. In FIG. 2, however, since jitter area 31 of the reproduced dot clock is positioned at a changing point of the video signal, nth signal 32 is sampled on a certain line, and (n+1)th signal 34 is sampled or changing point 33 is sampled on another line. As a result, the sampled image becomes indefinite. If the video signal and the reproduced dot clock are out of phase with each other, then the example shown in FIG. 2 occurs, and the sampled image becomes indefinite, resulting in a reduction in the displayed image quality. Particularly, flickering occurs at image edges due to the phase shift.
To solve the above problem, Patent Document 1 discloses a dot clock reproducing apparatus for determining the difference between the sampled values of adjust dots in a converted digital video signal, accumulatively adding the absolute values of the differences during one frame, and adjusting the phase of an output clock from a PLL circuit based on the accumulated sum of the absolute values of the differences during one frame. The disclosed dot clock reproducing apparatus determines a phase adjustment value at the time the accumulated sum of the absolute values of the differences is minimum, and automatically adjusts the phase of the reproduced dot clock so as to estimate a phase adjustment value that is ½ period shifted from the determined phase adjustment value, as an optimum value.
However, the disclosed dot clock reproducing apparatus disclosed in Patent Document 1 evaluates phase adjustment for each frame, and hence requires time-consuming processing because it needs to evaluate phase adjustment for several frames to several tens of frames in order to determine an optimum value for phase adjustment.
Generally, when a digital video signal is received from a video signal source, not only digital video signals of R, G, B and horizontal and vertical synchronizing signals, but also a dot clock, are supplied from the video source. Therefore, it is guaranteed that the frequency of the dot clock is optimum. However, if a very long cable which is not up to given standards is used to interconnect the video signal source and the image display apparatus or if the layout of components in the image display apparatus, i.e., the pattern of signal lines for transmitting a video signal and a dot clock, is not appropriate, then the dot clock and the digital video signal may possibly be out of phase with each other. Inasmuch as there is no guarantee that the digital video signal and the dot clock are in phase with each other, the displayed image quality may be degraded due to a phase shift between the digital video signal and the dot clock as is the case with the analog video signal.